Principal Engineer (Lead) | Micron Technology | San Jose, California, United States

With over 18 years of experience as a Semiconductor professional, I am specialized in the field of digital design verification and hardware emulation for SoCs and ASICs in the networking and storage space. As a principal lead at Micron, my responsibilities include managing the hardware emulation platform to enable pre-silicon product validation across multiple groups globally in the organization. Prior to Micron, I was a Lead Application Engineer at Cadence Design Systems, leading customer engagements to integrate and bringup EDA solutions on Cadence tools platform focused on design verification and validation.