Sr Physical Design Engineer | Nvidia | Santa Clara, California, United States

I have been in the hardware industry for past 7 years with experience in Silicon Engineering, VLSI and EDA tool industry. Groq: AI & ML Chip Startup which is radically simplifying heavy workloads with its disruptive architecture Experience driving execution of blocks from Synthesis, P&R to Timing Signoff, Physical Signoff and Electrical Signoff. Optimize and improve flows and overall RTL to GDS2 physical design methodology with a data driven approach. Nvidia: Leading GPU and CPU manufacturer in the world. Optimization and orchestration of physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and full chip level. Cadence Design Systems: Industry Leading EDA tool company Synthesized designs, logic optimization and timing analysis to help customer achieve their design goals and targets. Implemented placement, clock tree synthesis & routing and performed static timing analysis. Contributed to revenue generation of $10mn+ working on customer engagement and POCs leading to product tool upsells and cross-sells.